This invention relates to a chemical amplification (or chemically amplified) type [Kagakuzofuku-gata] photoresist composition, a method for producing a semiconductor device using the composition, and a semiconductor substrate. More particularly, it relates to a chemical amplification type photoresist composition for prohibiting resist pattern resolution defects, a method for producing a semiconductor device using the composition, and a semiconductor substrate.
Definition: The term xe2x80x9cchemical amplification (or chemically amplified) type photoresistxe2x80x9d used herein denotes a class of the photoresist that falls within the following category:
Chemical amplification type photoresist composition means a composition containing an acid generating agent as a sensitizer in the resist, generating acid therefrom upon light exposure, thus inducing the catalytic reaction by the generated acid during the subsequent heat treatment, thereby accelerating soluble or insoluble property against the developing solution.
As a method for forming multi-layered wirings for a semiconductor integrated circuit, buried wirings (Damascene techniques) is effective. In these techniques, the dual Damascene technique, consisting in forming a wiring trench for forming an upper layer wiring and a via hole or a contact hole interconnecting the upper layer wiring and a lower layer wiring or substrate in an insulating film, and in burying the same metal film in both the wiring trench and the via hole to form the interconnections and the via as one, gives rise to an advantage that production costs may be lowered appreciably through simplifying and expediting the production process.
On the other hand, a low dielectric constant film (Low-k film) has been brought into use as an inter-layer insulating film intermediate the wirings in the multilayer wiring structure, in order to diminish the capacitance across neighboring wirings to reduce signal delay through the wirings.
An instance of a conventional via first dual Damascene interconnection forming method is now explained.
First, a first etching barrier film 7, a first inter-layer insulating film 6, a second etching barrier film 5, a second inter-layer insulating film (low dielectric constant film) 4, and a cap film (insulating film) 3, are formed on an underlying Cu wiring layer 8, in this order, looking from the substrate side. An anti-reflection film then is coated on the entire substrate surface, and a first photoresist pattern for forming via-holes is deposited on the surface of the anti-reflection film. Using this first photoresist pattern as an etching mask, the anti-reflection film, cap film 3, second inter-layer insulating film 4, second etching barrier film 5 and the first inter-layer insulating film 6 are selectively continuously etched, until the first etching barrier film 7 is exposed. This forms a via-hole 21 (see FIG. 9a).
The anti-reflection film and the first photoresist pattern are then removed by ashing or an organic removing (peeling) liquid (see FIG. 9a). An anti-reflection film 2 then is formed on the entire substrate surface such that the via-hole 21 is not completely buried (see FIG. 9b). A photoresist 1 then is coated on the surface of the anti-reflection film 2 (see FIG. 9c). The coated photoresist is exposed to light to form a second photoresist pattern 1 for forming a wiring trench (see FIG. 9d). Using this second photoresist pattern as an etching mask, the anti-reflection film 2, cap film 3 and the second inter-layer insulating film 4 are selectively continuously etched until the second etching barrier film 5 is exposed (see FIGS. 9e and f). This forms a wiring trench 22.
The anti-reflection film 2 and the second photoresist pattern 1 are then peeled or removed by ashing or with an organic removing solution. The exposed first etching barrier film 7 then is etched by an etchback method until the underlying Cu wiring layer 8 is exposed (see FIG. 9g). The substrate, the underlying Cu wiring layer 8 of which has now been exposed, is rinsed. After forming a seed film and a metal barrier film on the substrate, a Cu plating film 9 is deposited until it is buried in the via-hole and in the wiring trench. The Cu plating film 9 and the cap film 3 are planarized by CMP (chemical mechanical polishing) until the cap film 3 is substantially ground off by polishing (see FIG. 9h). This forms a dual Damascene wiring 9 electrically connected to the lower Cu wiring layer 8 (See JP-P2001-217242A).
According to an experiment, conducted by the present inventors, if, with use of a conventional chemical amplification type photoresist composition (positive type) as the photoresist, the second photoresist pattern 1 is formed, the photoresist in the via-hole 21 and in the neighboring area is not decomposed, even on light exposure, such that the photoresist is left over even on processing with the developing solution (see FIG. 9d. The state of the substrate surface is shown in FIG. 3 as Comparative Example. Referring to respective patterns in the Comparative Example, the portions of the substrate, corresponding to the via-holes, are inherently represented in black as a shadow of the groove. In the present Comparative Example, there are those via-holes in which the black shadows by the groove are not represented such that the via-holes are charged with the photoresist buried therein.
According to the technical information, acquired by the present inventors, the reason this problem arises is that, if the anti-reflection film and the chemical amplification type photoresist composition are coated and exposed to light without pre-treatment (such as heating, UV processing or oxygen plasma processing), the pollutants, such as basic compounds or moisture, affixed to or soaked into the substrate surface (such as via-hole wall surface of the inter-layer insulating film), tend to be transmitted through the anti-reflection film at the time of baking the anti-reflection film and the photoresist (pre-baking for solvent removal) so as to be intruded into the photoresist.
That is, in the via first dual Damascene method, an organic alkaline removing solution is used to remove the resist pattern used for forming the via-hole. The pollutants contained in this organic removing solution, such as basic compounds (amino components), moisture in air or floating basic compounds, are affixed to or seep into the via-hole wall surface (inter-layer insulating film) where the pollutants are concentrated. If the anti-reflection film for the wiring groove and the photoresist (chemical amplification type positive photoresist composition) are then coated on the substrate surface, inclusive of the via-hole wall surface, and pre-baked, the pollutants concentrated on the via-hole wall surface are transmitted from the via-hole wall surface through the anti-reflection film so as to be intruded into the photoresist. The so intruded pollutants, such as amino compounds, are neutralized with catalytic acids (H+) yielded on light exposure due to photodecomposition of the acid generating agents contained in the photoresist (chemical amplification type positive photoresist composition). Should this neutralization reaction between the pollutants and the acid catalyst occur, the acid catalyst in the photoresist is deactivated and hence falls into shortage. This phenomenon is known as poisoning. The photoresist lying in an area where the acid catalyst is deactivated cannot be turned, even on light exposure, into a substance soluble in a developing solution (change in polarity). For example, protective groups, such as acetyl groups, cease to exhibit protective action such that the chain reaction into hydroxyl groups is scarcely produced. The area of the substrate which has not been turned into the developing solution, such as the inside of the via-hole or its vicinity, is left over without being dissolved in the developing solution. As a consequence, resolution defects of the resist pattern occur in the inside of the via-hole or its vicinity.
An experiment conducted by the present inventors revealed that, although a satisfactory resist pattern could be resolved with the conventional chemical amplification type photoresist, in the absence of the via-hole, in case development was carried out for 30 minutes under the condition in which the poisoning occurs, the poisoning occurs severely around the via-hole, such that the resist pattern suffers from resolution deficiency. Although the resistance against the poisoning can be improved by extending the development time duration to 60 seconds, the resolution was still insufficient.
Another experiment conducted by the present inventors also indicated that this problem (resolution defect) was more apparent when a low dielectric constant insulating film (Low-k film with the specific dielectric constant k less than 4.0) was used as the inter-layer insulating film in place of the conventional silicon oxide film. That is, such a problem has presented itself that, if the low dielectric constant insulating film is used, the area where the photoresist is left without becoming dissolved in the developing solution, that is the photoresist not resolved even on light exposure, is increased.
The inventor""s technical knowledge indicates that this problem is ascribable to the fact that, since the low dielectric constant film (low-k film) is a porous film presenting interstices in its molecular structure, in a majority of cases, this interstice (fine pores) in the molecular structure increasing with the tendency towards the low dielectric constant. Thus, more pollutants are liable to be affixed (adsorbed) or seep into the film than in case of a routine inter-layer insulating film (SiO2). The result is that the quantity of the pollutants intruded from the low dielectric constant film into the photoresist is larger than in case of the silicon oxide film to increase the area subjected to resolution defects of the resist pattern.
The photoresist, thus left, overlies the rim of the via-hole on the surface of the cap film 3, such that, when the wiring groove 22 is to be etched, the residual photoresist operates as a visor on the cap film 3, with the result that a protrusion 10 in the form of a tapered cylinder comprised of the cap film 3 and the second inter-layer insulating film 4 is formed around the outer rim of the via-hole (see FIG. 9g). If the low dielectric constant film (Low-k film) is used as the inter-layer insulating film, the protrusion 10 is increased in size. If the Cu dual Damascene wiring 9 is formed as the protrusion 10 is left over, separation or connection defects occur intermediate the wiring and the via-hole in the dual Damascene wiring 9, due to the protrusion 10, with the result that the electrical connection between the wiring and the via-hole in the dual Damascene wiring 9 is insufficient (see FIG. 9h). The result is the lowered reliability of the semiconductor device.
It is a primary object of the present invention to provide a method for producing a semiconductor device suited to resist patterning of a substrate presenting surface step differences.
It is a second object of the present invention to provide a method for producing a semiconductor device suited to resist patterning of a substrate having low dielectric constant.
It is a third object of the present invention to provide a method for producing a semiconductor device which lends itself to simplification and speedup of the manufacturing process.
It is a fourth object of the present invention to provide a semiconductor substrate having an optimum resist pattern formed thereon.
It is a fifth object of the present invention to provide a chemical amplification type positive photoresist composition which may be suitably used for the method for producing the semiconductor device.
In a first aspect, the present invention provides a method for producing a semiconductor device including the steps of forming a resist film on a substrate, using a chemical amplification type photoresist composition comprised of a base resin and a basic compound added to the base resin in a range of not less than 1 mmol to not more than 100 mmol to 100 g of the base resin, and exposing a predetermined area of the resist film to light to form a resist pattern.
In a second aspect, the present invention provides a method for producing a semiconductor device including the steps of forming a resist film on a substrate, having a hole or a trench formed in a surface thereof, using a chemical amplification type photoresist composition comprised of a base resin and a basic compound added to the base resin in a range of not less than 1 mmol to not more than 100 mmol to 100 g of the base resin, and exposing a predetermined area of the resist film to light to form a resist pattern.
In a third aspect, the present invention provides a method for producing a semiconductor device including the steps of removing from a substrate, etched using a first resist pattern, the first resist pattern, using at least an organic removing solution, and forming a resist film on the substrate, from which the first resist pattern has been removed, using a chemical amplification type photoresist composition comprised of a base resin and a basic compound added to the base resin in a range of not less than 1 mmol to not more than 100 mmol to 100 g of the base resin, and exposing a predetermined area of the resist film to light to form a second resist pattern.
In a fourth aspect, the present invention provides a method for producing a semiconductor device including the steps of: removing from a substrate, having a via-hole formed therein using a first resist pattern, the first resist pattern, using at least an organic removing solution, and forming a resist film on a substrate, having a via-hole formed therein, using a chemical amplification type photoresist composition comprised of a base resin and a basic compound added to the base resin in a range of not less than 1 mmol to not more than 100 mmol to 100 g of the base resin, and exposing a predetermined area of the resist film to light to form a second resist pattern used for forming a wiring groove.
In a fifth aspect, the present invention provides a chemical amplification type photoresist composition comprising a base resin and a basic compound added to the base resin in a range of not less than 1 mmol to not larger than 100 mmol to 100 g of the base resin.
Preferably, the substrate is (1) such a substrate in which one or more porous films are exposed on a surface or a sidewall surface, (2) such a substrate in which one or more porous films are exposed on a surface or a sidewall surface, or (3) such a substrate in which one or more low dielectric films with a specific dielectric constant less than 4 are exposed on a surface or a sidewall surface
Preferably, the chemical amplification type photoresist composition is such a chemical amplification type photoresist composition which is comprised of a base resin and a basic compound added to the base resin in a range of not less than 2 mmol to not more than 50 mmol to 100 g of the base resin.
Preferably, the chemical amplification type photoresist composition which is comprised of a base resin and an acid generating agent added to the base resin in a range of not less than 0.2 weight parts to not more than 20 weight parts and in particular 0.5 weight parts and not larger than 10 weight parts of the base resin.
Preferably, the resist pattern or the second resist pattern in the method for producing a semiconductor device includes an opening in an area of the substrate including a sidewall surface in a step difference portion thereof.
Preferably, a predetermined area of the resist film in the method for producing a semiconductor device is exposed to light and subsequently developed for not less than 30 seconds and in particular for not less than 60 seconds using a developing solution.
In a sixth aspect, the present invention also provides a semiconductor substrate including a resist pattern formed by the method for producing the semiconductor device.
FIGS. 1a-1h are partial cross-sectional views illustrating, step-by-step, a method for manufacturing a semiconductor device according to Example 1 of the present invention.
FIG. 2, includes two graphs illustrating the results of identifying the components affixed to a substrate having a Low-k film following the step A6 of Example 1, by the capillary electrophoretic method.
FIG. 3 is an enlarged photo showing, for comparison, the states of the substrate surface following the process of forming a resist pattern for forming the wiring groove in the manufacturing methods for the semiconductor device of the Example 1 and the Comparative Example.
FIG. 4 is a comprehensive graph showing an intensity curve for detected poisoning components desorbed from the substrate having the Low-k film after step A6 of Example 1, against time, and the gradually rising temperature, in case the temperature is increased gradually.
FIG. 5 is a comprehensive graph showing an intensity curve for detected poisoning components desorbed from the substrate having the Low-k film after step A6 of Example 1, against time, and the rising temperature, in case the temperature is increased rapidly up to 400xc2x0 C. at which the temperature then is kept constant.
FIG. 6 is an enlarged photo showing the states of the substrates following the process of forming the resist pattern for forming the wiring groove in the method for manufacturing the semiconductor device of Example 1 and the Comparative Example 1 (substrate 1, samples 1 to 6).
FIG. 7 is an enlarged photo showing the states of the substrates following the process of forming the resist pattern for forming the wiring groove in the method for manufacturing the semiconductor device of Example 1 and the Comparative Example 1 (substrate 2, samples 1 to 6).
FIGS. 8a-8h are partial cross-sectional views showing the states of the substrate for respective steps of he method for manufacturing the semiconductor device of Example 1 step by step.
FIGS. 9a-9h are partial cross-sectional views showing the states of the substrate for respective steps of the method for manufacturing the semiconductor device of Comparative Example step by step.